Digital Electronics — DSSSB TGT CS Notes
Must-know bullets, tables, and MCQ traps. Concise exam focus.
1. Number Systems
| System | Base | Digits |
|---|---|---|
| Binary | 2 | 0, 1 |
| Octal | 8 | 0–7 |
| Decimal | 10 | 0–9 |
| Hexadecimal | 16 | 0–9, A–F |
Quick conversion methods
- Binary → Decimal: sum of (bit × 2^weight).
- Decimal → Binary: repeated divide by 2; remainders bottom-up.
- Binary ↔ Octal: group bits in 3s (from LSB).
- Binary ↔ Hex: group bits in 4s (from LSB).
- Octal/Hex ↔ Decimal: via binary or place values.
Examples to memorise pattern:
- (1010_2 = 10_)
- (FF_{16} = 255_)
- (17_8 = 15_)
Trap: Hex A=10 … F=15. Leading zeros in grouping don’t change value but matter for bit length questions.
2. 1’s and 2’s Complement (binary)
Used for representing signed integers and subtraction.
| Form | How obtained | Notes |
|---|---|---|
| 1’s complement | Invert all bits | +0 and −0 both exist |
| 2’s complement | 1’s complement + 1 | Unique zero; standard in computers |
Range (n-bit 2’s complement): (-2^{n-1}) to (2^{n-1}-1).
Example 8-bit: −128 to +127.
Subtraction tip: A − B = A + (2’s complement of B); discard end carry for fixed width.
Trap: “Invert bits” alone = 1’s complement, not 2’s. MSB=1 usually means negative in 2’s complement.
3. Boolean Algebra — Laws (must-know)
| Law | Form |
|---|---|
| Identity | A + 0 = A ; A · 1 = A |
| Null / Domination | A + 1 = 1 ; A · 0 = 0 |
| Idempotent | A + A = A ; A · A = A |
| Complement | A + A′ = 1 ; A · A′ = 0 |
| Commutative | A + B = B + A ; A · B = B · A |
| Associative | (A+B)+C = A+(B+C) |
| Distributive | A(B+C)=AB+AC ; A+BC=(A+B)(A+C) |
| Absorption | A + AB = A ; A(A+B)=A |
| Double negation | (A′)′ = A |
De Morgan’s theorems
- ((A + B)' = A' · B')
- ((A · B)' = A' + B')
Trap: De Morgan flips operator and complements each variable. NAND is universal; NOR is universal.
4. Logic Gates & Truth Tables
| Gate | Output | Notes |
|---|---|---|
| AND | 1 only if all inputs 1 | · |
| OR | 1 if any input 1 | + |
| NOT | Invert | ′ or bar |
| NAND | NOT-AND | Universal |
| NOR | NOT-OR | Universal |
| XOR | 1 if inputs differ | ⊕ ; odd parity for 2 inputs |
| XNOR | 1 if inputs same | Equivalence |
2-input quick table (memorise XOR/XNOR)
| A | B | AND | OR | XOR | XNOR | NAND | NOR |
|---|---|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 |
| 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 |
Trap: XOR is not OR. XNOR = XOR′.
5. SOP and POS (brief)
- SOP (Sum of Products): OR of AND terms → e.g. (AB + A'C). From truth table: minterms where output = 1.
- POS (Product ofSums): AND of OR terms → e.g. ((A+B)(A'+C)). Maxterms where output = 0.
- Canonical SOP: all variables in each product (minterms).
- Canonical POS: all variables in each sum (maxterms).
Trap: Minterm ↔ output 1; Maxterm ↔ output 0.
6. Half Adder & Full Adder
Half adder (2 bits: A, B)
- Sum = A ⊕ B
- Carry = A · B
- No carry-in.
Full adder (A, B, Cin)
- Sum = A ⊕ B ⊕ Cin
- Carry = Majority: AB + BCin + ACin
Can be built from two half adders + OR.
Trap: Half adder cannot add carry from previous stage; full adder can.
7. Flip-Flops (basics)
Sequential elements store 1 bit; clocked versions are edge-triggered FFs.
| FF | Characteristic | Notes |
|---|---|---|
| SR | Set / Reset | Invalid when S=R=1 (basic latch) |
| JK | Like SR without invalid | J=K=1 → toggle |
| D | Q follows D | Delay / data FF; no illegal input |
| T | Toggle if T=1 | T=0 hold; T=1 toggle |
Race condition: In level-sensitive latches / asynchronous SR, if inputs change such that feedback races, output can become unpredictable (e.g., SR=11 then both go 0). JK designed to avoid SR invalid; still care with timing (master-slave / edge trigger).
Trap: D flip-flop is most common for registers. T is for counters. “Race around” often linked to JK in level-triggered discussion (exam phrase).
8. MUX, DEMUX, Encoder, Decoder
| Device | Function |
|---|---|
| Multiplexer (MUX) | Many inputs → one output (select lines choose) |
| Demultiplexer (DEMUX) | One input → many outputs |
| Encoder | 2ⁿ inputs → n-bit code (e.g. octal to binary) |
| Decoder | n-bit code → 2ⁿ outputs (e.g. 3-to-8) |
- n select lines → 2ⁿ MUX inputs (e.g. 8:1 needs 3 selects).
- Decoder often used for chip select / memory addressing.
Trap: MUX ≠ encoder. Encoder compresses active input to code; MUX selects which data path passes.
Quick MCQ Checklist
- Group-by-3 / group-by-4 for octal/hex.
- 2’s = invert + 1; unique zero.
- De Morgan: bubble and change + ↔ ·.
- NAND/NOR universal; XOR for odd parity / adders.
- Half: Sum XOR, Carry AND; Full adds Cin.
- JK toggle on 11; SR 11 forbidden (basic).
- MUX many→1; DEMUX 1→many; Decoder n→2ⁿ.
- Race: unpredictable due to timing/feedback in latches.